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rev. 1.0 january 2019 www.aosmd.com page 1 of 20 AOZ2140DI 5.5v/3a synchronous ezbuck? regulator and smart load switch general description the AOZ2140DI is a high-eff iciency, easy-to-use dc/dc synchronous buck regulator which supports 3v to 5.5v input voltage range. the device is capable of supplying 3a of continuous output cu rrent with an output voltage adjustable down to 0.8v (1.0%). a proprietary constant on-time pwm control with input feed-forward results in ultra-fast transient response while maintaining relatively 650khz constant switching frequency over the entire input voltage range. the device features multiple protection functions such as v cc under-voltage lockout, c ycle-by-cycle current limit, output over-voltage protection, short-circuit protection, and thermal shutdown. the AOZ2140DI also integrates a signal channel load switch with typical 23m ? on-resistance in a small pack- age. it contains one n-channel mosfet for up to 5.5v input voltage operation and 5a of continuous output current. the AOZ2140DI integrates an internal 290 ? load resistor for quick output discharge when load switch is off. the AOZ2140DI is available in a 3mm2mm dfn-14l package and is rated over a -40c to +85c ambient temperature range. features ezbuck?:? 3v to 5.5v input voltage range ? 3a continuous current per channel ? output voltage adjustable down to 0.8v 1.0% ? internal r ds(on) pfet and nfet C 140m ? high-side pfet C 45m ? low-side nfet ? fixed switching frequency is 650khz ? ceramic capacitor stable ? cycle-by-cycle current limit ? short-circuit protection ? over voltage protection ? thermal shutdown smart load switch: ? 0.8v to 5.5v input voltage range ? 5a continuous output current ? low r ds(on) nfet C 23m ? ? integrated quick output discharge resistor ? thermally enhanced 3mm x 2mm dfn-14l package applications ? portable computers ? compact desktop pcs ? set top boxes ? lcd tvs ? cable modems ? point of load dc/dc converters ? telecom/networking/datacom equipment downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 2 of 20 typical application start-up sequence AOZ2140DI c1 10fx2+0.1f en1 lx fb gnd vcc pgnd in2 en2 out in1 off on c3 4.7f 5v vout 2/5a c5 1f off on c4 10f c2 22fx2 vout1 0.8v to 0.85*in1 input2 0.8v to 5.5v l1 0.56h power ground analog ground input1 3v to 5.5v in1 or in2 v cc en1 or en2 50us 4ms v out1 t on v out2 downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 3 of 20 ordering information all aos products are offered in packages with pb-f ree plating and compliant to rohs standards. please visit www.aosmd.com/media/aosgreenpolicy.pdf for additional information. pin configuration part number temperature range package environmental AOZ2140DI -40c to +85c 3mmx2mm dfn-14l green pin description pin number pin name pin function 1, 2 pgnd power ground. 3, 4 lx converter switching node. 5 en2 enable input for smart load switch which is on when en2 is pulled high and is off when en2 is pulled low. do not floating this pin. 6, 7 out smart load switch output. 8, 9 in2 supply input for smart load switch. all in2 pins must be connected together. 10 vcc supply input for analog functions. bypass vcc to gnd with a 1f~10f ceramic capaci- tor. place the capacitor as close to vcc pin as possible. 11 fb feedback input for converter. adjust the output voltage with a re sistive voltage-divider between the regulator's output and gnd. 12 en1 enable input for converter. converter is enabled when en1 is pulled high. the converter shuts down when en1 is pulled low. 13, 14 in1 supply input for converter. all in1 pins must be connected together. epad exposed pad the exposed bottom pad must be c onnected to gnd. this is also agnd of ic. 1 45 10 11 12 pgnd pgnd en1 en2 in2 in2 out out vcc fb gnd lxlx in1 in1 23 6 7 1413 98 14-pin 3mm x 2mm dfn (top view) downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 4 of 20 electrical characteristics ezbuck? t a = 25c, v in =5v, v cc =5v, en = 5v, unless otherwise specified. specifications in bold indicate a temperature range of -40c to +85c. symbol parameter conditions min. typ. max. units v in1 in1 supply voltage 3 5.5 v v uvlo under-voltage lockout threshold of v cc v cc rising v cc falling 2.4 2.8 2.55 3v v v cc_hys v cc uvlo hysteresis 180 mv i q quiescent supply current i out = 0a, v en1 = 5v, v en2 = 0v 150 a i off shutdown supply current v en1 = v en2 = 0v 100 na v fb feedback voltage t a = 25c t a = 0c to 85c 0.792 0.788 0.8000.800 0.8080.812 vv load regulation 0.5 % line regulation 1% i fb fb input bias current 10 na enable v en1 en1 input threshold off threshold on threshold 1.4 0.5 v v en1_hys en1 input hysteresis 200 mv modulator t on on time v in =5v=v cc , v out =1v 310 ns t on _ min minimum on time 200 ns t off _ min minimum off time 310 ns soft-start t ss _ out ss source time 4m s absolute maximum ratings exceeding the absolute maximum ratings may damage the device. notes: 1. lx to pgnd transient (t<20ns) ------- -5v to v in +5v. 2. devices are inherently esd sens itive, handling precautions are required. human body model rating: 1.5k in series with 100pf recommend operating ratings the device is not guaranteed to operate beyond the maximum operating ratings. parameter rating in1, in2, lx to pgnd (1) -0.3v to 6v vcc, fb, en1, en2, to agnd -0.3v to 6v pgnd to agnd -0.3v to +0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating hbm/cdm (2) 2kv/1kv parameter rating supply voltage (v in ) 3v to 5.5v supply voltage (v in2) 0.8v to 5.5v output voltage range v out1 0.8v to 0.85*v in ambient temperature (t a ) -40c to +85c package thermal resistance 3x2 dfn-14 ( ? jc ) 3x2 dfn-14 ( ? ja ) 10c/w 65c/w downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 5 of 20 AOZ2140DI electrical characteristics (continued) ezbuck? t a = 25c, v in =5v, v cc =5v, en = 5v, unless otherwise specified. spec ifications in bold indicate a temperature range of -40c to +85c . smart load switch t a = 25c, v cc = 5v, unless otherwise specified . symbol parameter conditions min. typ. max. units under voltage and over voltage protection v pl under voltage threshold fb falling 70 % t pl under voltage delay time 20 us v ph over voltage threshold fb rising 120 % power stage output r dsh(on) high-side pfet on- resistance vin = 5vvcc = 5v 140 m ? high-side nfet leakage ven = 0v, vlx = 0v 10 10 ua r dsl(on) low-side nfet on- resistance vlx = 5vvcc = 5v 45 m ? low-side nfet leakage ven = 0v 10 ua over-current and thermal protection over current vcc = 5v 5 a thermal shutdown threshold 150 c symbol parameter conditions min. typ. max. units v in2 in2 supply voltage 0.8 5.5 v v cc vcc supply voltage 3 5.5 v v uvlo under-voltage lockout threshold of v cc v cc rising v cc falling 2.4 2.8 2.55 3 v i d maximum continuous current v in2 = v en2 = 5v 5a i pls maximum pulsed switch current v in2 = v en2 = 5v pulse < 300 s, 2% duty cycle 7a i q quiescent supply current of v cc i out = 0a v in2 = 5v, v en1 =0v, v en2 = 5v 150 ua i off shutdown supply current v en1 = v en2 = 0v 100 na i en2 en2 leakage current 1u a v enh2 en2 high level voltage 1.4 v v enl2 en2 low level voltage 0.5 v en2_hys en2 input hysteresis 200 mv switching on resistance r on switch on-state resistance i out = -200ma v in2 = 0.8v to 5v 23 m ? r pd output pull-down resistance i out = 15ma v in2 = 5v, v en2 = 0v 290 ? downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 6 of 20 AOZ2140DI switching characteristics test conditions: t a = 25c, c 4 =1uf, c 5 =0.1uf, r lout2 =10 ? , unless otherwise specified. symbol parameter conditions min. typ. max. units vin2=vcc=5v t on turn-on time 310 s t d-on turn-on delay time 110 s t r turn-on rise time 464 s t off turn-off time 1.97 s t f turn-off fall time 2.25 s vin2=2.5v, vcc=3v t on turn-on time 241 s t d-on turn-on delay time 150 s t r turn-on rise time 206 s t off turn-off time 5.26 s t f turn-off fall time 3 s vin2=0.8v, vcc=3v t on turn-on time 172.5 s t d-on turn-on delay time 148.8 s t r turn-on rise time 45.5 s t off turn-off time 15.5 s t f turn-off fall time 2.85 s en2 vout2 50% 1% t on t d_on 10% 90% 50% t r 10% 90% 50% t f t off 50% downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 7 of 20 functional block diagram + sr q timer q toff_min fb 0.8v ilim error comp ilim comp timer q ton vcc in1 lx pgnd vcc gnd current information processing isense isense (ac) isense isense (ac) uvlo en1 otp fb decode out reference & bias control logic charge pump in2 en2 vcc downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 8 of 20 typical performance characteristics ezbuck? t a =25 o c, v in =5v, v out =1v, unless othe rwise specified. normal operation v o ripple (20mv/div) v lx (4v/div) i lx (2a/div) load transient 0a to 3a v o (100mv/div) i lx (2a/div) full load start-up v o (400mv/div) en (5v/div) v lx (4v/div) i lx (2a/div) short circuit protection v o (400mv/div) v lx (4v/div) i lx (3a/div) efficiency (%) output current (a) efficiency vs. load current 01 23 9590 85 80 75 70 65 60 55 50 vo=3.3v vo=2.5v vo=1.8v vo=1v downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 9 of 20 typical performance characteristics lds turn-on & turn-on rise times (v in2 =5v,v cc =5v,c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) v out (2v/div) en (3v/div) turn-on & turn-on rise times (v in2 =0.8v,v cc =5v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) v out (400mv/div) en (3v/div) turn-on & turn-on rise times (v in2 =2.5v,v cc =3v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) en (3v/div) v out (800mv/div) turn-on & turn-on rise times (v in2 =0.8v,v cc =3v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) en (3v/div) v out (400mv/div) turn-off & turn-off fall times (v in2 =5v,v cc =5v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) en (3v/div) v out (2v/div) turn-off & turn-off fall times (v in2 =0.8v,v cc =5v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) en (3v/div) v out (400mv/div) downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 10 of 20 AOZ2140DI typical performance characteristics lds turn-off & turn-off fall times (v in2 =2.5v,v cc =3v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) en (3v/div) v out (800mv/div) turn-off & turn-off fall times (v in2 =0.8v,v cc =3v, c 4 =1uf,c 5 =0.1uf,r lx =10 ? ) en (3v/div) v out (400mv/div) turn-on & turn-off @ iout=3a (v in2 =5v,v cc =5v,c 4 =4.7uf,c 5 =4.7uf) en (3v/div) v out (2v/div) i out (2a/div) turn-on & turn-off @ iout=3a (v in2 =0.8v,v cc =3v,c 4 =4.7uf,c 5 =4.7uf) en (3v/div) v out (400mv/div) i out (2a/div) downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 11 of 20 AOZ2140DI typical characteristics lds t on vs. v in (v cc =3v) t d-on vs. v in (v cc =5.5v) t on vs. v in (v cc =5.5v) t r vs. v in (v cc =3v) t d-on vs. v in (v cc =3v) t r vs. v in (v cc =5v) ton( s) vin (v) 0.8 1.6 500 450 400 350 300 250 200 150 100 50 0 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c - 40oc 25oc 80oc td-on( s) vin (v) 0.8 1.6 150 140 130 120 110 100 9080 70 60 50 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c ton( s) vin (v) 0.8 1.6 400 350 300 250 200 150 100 50 0 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c tr( s) vin (v) 0.8 1.6 800 700 600 500 400 300 200 100 0 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 - -40oc 25oc 80oc \ 40 ? c 25 ? c 80 ? c td-on( s) vin (v) 0.8 1.6 200 190 180 170 160 150 140 130 120 110 100 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c ton( s) vin (v) 0.8 1.6 800 700 600 500 400 300 200 100 0 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 12 of 20 AOZ2140DI typical characteristics lds t off vs. v in (v cc =3v) t f vs. v in (v cc =5.5v) t off vs. v in (v cc =5.5v) r dson vs. v in (v cc =5.5v, i out =200ma) t f vs. v in (v cc =3v) r dson vs. v in (v cc =3v, i out =200ma) toff( s) vin (v) 0.8 1.6 2018 16 14 12 10 86 4 2 0 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c tf( s) vin (v) 0.8 1.6 4 3.5 3 2.5 2 1.5 1 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c ton( s) vin (v) 0.8 1.6 2520 15 10 50 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c vin (v) 0.8 1.6 3533 31 29 27 25 23 21 19 17 15 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c tf( s) vin (v) 0.8 1.6 4 3.5 3 2.5 2 1.5 1 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c vin (v) 0.8 1.6 3533 31 29 27 25 23 21 19 17 15 2.8 5.6 1.2 22.4 3.2 3.6 4 4.4 4.8 5.2 \ 40 ? c 25 ? c 80 ? c downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 13 of 20 AOZ2140DI detailed description the AOZ2140DI is a multi-function product which includes one ezbuck converter and one smart load switch. the converter of AOZ2140DI is a high-efficiency, easy- to-use dc/dc synchronous buck regulator optimized for notebook computers. the regulator is capable of supply- ing 3a of continuous output current with an output volt- age adjustable down to 0.8v. the input voltage of AOZ2140DI can be as low as 3v. the highest input voltage of AOZ2140DI can be 5.5v. constant on-time pwm with input feed-forward control scheme results in ultra-fast transient response while maintaining relatively constant switching frequency over the entire input range. true ac current mode control scheme guarantees the regu lators can be stable with ceramics output capacitor. protection features include v cc under-voltage lockout, curr ent limit, output over volt- age and under voltage protecti on, short-circuit protection, and thermal shutdown. the smart load switch of AOZ2140DI is enabled when en2 pin is on active high with 1.4v or above voltage. the smart load switch is disabled when the en2 pin is lower than 0.5v. the AOZ2140DI is available in a 14-pin 3mm2mm dfn package. enable and soft - start the converter of AOZ2140DI has internal soft-start fea- ture to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft-start pro- cess begins when v cc rises to 2.8v and voltage on en1 pin is high. an internal current source charges the inter- nal soft-start capacitor; the fb voltage follows the voltage of soft-start (v ss ) when v ss is lower than 0.8v. when v ss is higher than 0.8v, the fb voltage is regulated by internal precise band-gap voltage (0.8v). ss_ok will be high when v ss ramps up to 1.2v, as fig 1. the soft-start time typical is 4ms from en1 to v out1 settling. uvp and ocp enable after ss_ok is high. figure 1. soft start timing of AOZ2140DI constant on-time pwm control with input feed- forward the control algorithm of AOZ2140DI is constant on-time pwm control with input feed-forward. the simplified control schemati c is shown in fig 2. the high-side switch on-time is determined solely by a one- shot whose pulse width is determined by one internal resistor and is inversely proportional to input voltage (in1). the one-shot is triggered when the internal 0.8v is higher than the combined information of fb voltage and the ac current information of inductor, which is pro- cessed and obtained through the sensed low-side mos- fet current once it turns-on. the extra ac current information can help the stability of constant on - time con- trol even with pure mlcc app lication, which has very low esr. besides, the ac current information doesn't have dc component so there is no offset when output load is changed. it is fundamentally different from other v 2 constant on - time control schemes. figure 2. simplified cont rol schematic of AOZ2140DI true current mode control pure mlcc solution is po pular for dc/dc applications due to small size, good performance at high frequency, low esr and esl, and so on. however, the constant on- time control is easy to happen double pulses or multiple pulses in using pure mlcc solution. because there is a phase lag between output voltage ripple and inductor current ripple and it get worst with low esr application. v ss v out1 en1 v ss =0.8v v ss =1.2v ss_ok 0.8v fb voltage /ac current information comp programmable one-shot in1 pwm + - downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 14 of 20 the converter of AOZ2140DI senses the low-side mos- fet current and processes it into dc and ac items by using aos proprietary technique. the ac current infor- mation is injected on the fb pin in phase. and hence, the stability of constant on-time control can work stable with low esr of output capacitor and has better noise immu- nity. current-limit protection the AOZ2140DI has the current limit protection by using r ds(on) of the low-side mosfet to be as a current sens- ing. in order to get real current signal, a minimum con- stant off-time is implemented after the on - time. the threshold of current limit is about 5a of inductor valley current. if the current exceeds the current limit threshold, the pwm controller is not allowed to pulse one-shot . the current limit will keep the low- side mosfet turn-on until the current in the low-side mosfet is smaller than the current limit threshold . output current over -current protection the AOZ2140DI considers this is a true failed condition when ocp (inductor valley current=5a) is triggered con- tinuously 20us. after that, AOZ2140DI will be turned-off high-side and turned-on low-side mosfets until induc- tor current goes to zero. output voltage under-voltage protection there are two uvp thresholds. one is 70% of output volt- age and the other is 50% of ou tput voltage. the former is with a 20us delay to preven t false trigger. high-side will be turned-off and low-side will be turned-on until inductor current reaches zero current. please note, there is no uvp function during soft-start. output voltage over -voltage protection the threshold of ovp is 1.2 times of output voltage. when the output voltage exceeds the ovp threshold, high-side mosfet is turned-off and low-side mosfets is turned-on until inductor current downs to zero. over temperature protection AOZ2140DI provides an over temperature protection function when the junction temperature is higher than 150 ? c. both two outputs will be latched when otp is trig- gered. applications information the basic AOZ2140DI application circuit is shown in the first page. the related components selection and suitable input/output voltage range are explained as below sec- tions. input capacitor selection for the converter of AOZ2140DI, the input capacitors must be connected between in1 pins and pgnd pins. the input ripple voltage can be derived as: therefore, c in can be obtained by request input voltage ripple and related parameters. since the input current is pulsating in the buck converter, the current stress of the input capacitor should be considered when selecting the capacitor. for the buck converter, the rms value of the input capacitor current can be calculated by: let m equal the conversion ratio: the relation between the input capacitor rms current and voltage conversion ratio is calculated and shown in fig. 3. it can be obtained that when v o is a half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5i o . figure 3. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin-rms at worst operating conditions. ceramic capacitors are preferred for input capacito rs because of their low esr and high ripple current rating. depending on the applica- in o in o in o in v v v v c f i v ? ? ? ? ? ? ) 1( ) 1( _ in o in o o rms cin v v v v i i ? ? ? m v v in o ? 0.50.4 0.3 0.2 0.1 0 o m i i rms cin )( _ m downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 15 of 20 AOZ2140DI tion circuits, other low esr tantalum capacitor or alumi- num electrolytic capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors are preferred for better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures is based on certain amount of life time and more capacitors are needed when input voltage is low a pplication. further de-rating may be necessary for practical design requirement. for the load switch of AOZ2140DI, a capacitor of 1uf or higher value is recommended to place close to the in2 pins. this capacitor can reduce the voltage drop caused by the in-rush current during the turn-on transient of the load switch. a higher capacitance can be used to further reduce the voltage drop during high-current application. inductor the inductor is used to supply a constant current to the output when it is driven by a switching voltage. for given input and output voltage, inductance and switching fre- quency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low rip- ple current reduces inductor co re losses. it also reduces rms current through inductor and switches, which results in less conduction loss. usually, a peak to peak ripple current on the inductor is designed to be 30% to 50% of the output current. when selecting the inductor, make su re it is able to handle the peak current without saturation even at the highest oper- ating temperature. there is a highest current rms in the inductor in the buck converter. the conduction loss on the inductor needs to be checked for thermal and efficiency consider- ation. surface mount inductors in different shape and styles are available from capacitor vendors. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on the emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and rip- ple current rating. the selected output capaci tor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be consid- ered for long term reliability. output ripple voltage specif ication is another important factor for selecting the output capacitor. in a buck con- verter, the output ripple voltage is determined by the inductor value, switching fr equency, output capacitor value and esr. it can be calculated by the equation below: where c o is the output capacitor value and esr co is the equivalent series resistor of output capacitor. when the low esr ceramic capacitor is used as the out- put capacitor, the impedance of the capacitor at the switching frequency dominates. the output ripple is mainly caused by the capacitor value and inductor ripple current. the output ripple voltage calculation can be sim- plified to: if the impedance of esr at switching frequency domi- nates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output rip- ple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operat- ing temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, output capacitor current is continu- ous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calcu- lated by: ) 1( in o o l v v l f v i ? ? ? ? ? 2 l o lpeak i i i ? ? ? ) 8 1 ( o co l o c f esr i v ? ? ? ? ? ? ? o l o c f i v ? ? ? ? ? ? 8 1 co l o esr i v ? ? ? ? 12 _ l rms co i i ? ? downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 16 of 20 AOZ2140DI usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and induc- tor ripple current is high, the output capacitor could be overstressed. for the smart load switch, a capacitor of 0.1uf or higher value is recommended to place between the out2 pins and gnd. the switching times are affected by the capac- itance. a larger capacitor makes the initial turn-on tran- sient smoother. in order to prevent the output voltage droop, this capacitor must be large enough to supply a fast transient load. output voltage regulation performance as well known, off-time is used to compensate power loss in constant on-time topology. in order to avoid switching frequency is too hi gh and stability issue, off- time usually has a minimum value. therefore, regulation performance of output voltage is limited through mini- mum off-time, as shown in fig.4. for an example to explain clearly, the regulation of 4.5v to 3.3v is good when io 1a. if it operates with io>1a, the output voltage is decreased with io is increased due to minimum off- time limitation. please note that the results of fig.4 oper- ate in force ccm condition and the results are changed with different power loss. figure 4. output voltage regulation performance thermal considerations and layout considerations in the AOZ2140DI buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacito rs, to the vin pin, to the lx pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is turned-on. the second loop starts from the inductor, to the output capacitors and load, to the low side switch. current flows in the second loop when the low side low side switch is turned-on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is strongly recommended to connect input capaci- tor, output capacitor, gnd, and pgnd pin of the AOZ2140DI. in the AOZ2140DI buck regulator circuit, the major power dissipating components are the AOZ2140DI and the out- put inductor. the total power dissipation of the converter circuit can be measured by input power minus output power. the power dissipation of the inductor can be approxi- mately calculated by the dcr of the inductor and the out- put current. the actual junction temper ature can be calculated with the power dissipation in the AOZ2140DI and thermal impedance from junction to ambient. the maximum junction temperature of the AOZ2140DI is 150oc, which limits the maximu m load current capability. the thermal performance of the AOZ2140DI is strongly affected by the pcb layout. extra care should be taken by users during the design process to ensure that the ic will operate under the reco mmended environm ental con- ditions. 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 03 0.5 1 1.5 2 2.5 i o (a) v o (v) dcr of inductor=7m ? 5v to 3.3v 4.5v to 3.3v 4.2 to 3.3v 3.6v to 3.3v 3v to 1.8v 3.3v to 2.5v 3v to 2.5v ) ( ) ( 2 2 1 1 2 2 1 1 _ o o o o in in in in loss total i v i v i v i v p ? ? ? ? ? ? ? ? 1.1 2 _ ? ? ? inductor o loss indcutor r i p ja loss inductor loss total junction p p t ?? ? ? ) ( _ _ downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 17 of 20 layout considerations several layout tips are listed below for the best electric and thermal performance. 1. the lx pins and pad are connected to internal low side switch drain. they are low resistance thermal conduction path and most noisy switching node. connected a large copper plane to lx pin to help thermal dissipation. 2. the in pins and pad are connected to internal high side switch drain. they ar e also low resistance ther- mal conduction path. connected a large copper plane to in pins to help thermal dissipation. 3. input capacitors should be connected to the in pin and the pgnd pin as close as possible to reduce the switching spikes. 4. decoupling capacitor c vcc should be connected to v cc and agnd as close as possible. 5. voltage divider r1 and r2 should be placed as close as possible to fb and agnd. 6. a ground plane is prefer red; pgnd and agnd must be connected to the ground plane through vias. 7. keep sensitive signal traces such as feedback trace far away from the lx pins. 8. pour copper plane on all unused board area and connect it to stable dc nodes, like vin, gnd or vout. 1 45 10 11 12 pgnd pgnd en1 en2 in2 in2 out out vcc fb agnd lx lx in1 23 67 14 13 9 8 in1 c in c out1 l v out1 downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 18 of 20 package dimensions , dfn3x2a-14l, ep1_s downloaded from: http:///
rev. 1.0 january 2019 www.aosmd.com page 19 of 20 AOZ2140DI tape and reel dimens ions, dfn3x2a-14l, ep1_s downloaded from: http:///
AOZ2140DI rev. 1.0 january 2019 www.aosmd.com page 20 of 20 package marking AOZ2140DI (dfn3x2-14) lt yw assembly lot code part number code option code assembly location code 0a bs week & year code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provi ded in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. legal disclaimer alpha and omega semiconductor makes no representati ons or warranties with respect to the accuracy or completeness of the information provided herein and takes no liabilities for the c onsequences of use of such information or any product described herein. alpha and omega semiconductor reserves the right to make changes to such information at any time without further notice. this document does not constitute the grant of any intellectual property rights or representation of non-infringeme nt of any third partys intellectual property rights. life support policy alpha and omega semiconduct or products are not auth orized for use as critical components in life su pport devices or systems. downloaded from: http:///

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